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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-10-31 10:29:51 +0100 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2024-11-04 10:59:12 -0800 |
| commit | 929d8490f8790164f5f63671c1c58d6c50411cb2 (patch) | |
| tree | 7d3e2b832726e324e7d324643e693aefb50c611a /tools/perf/scripts/python/syscall-counts.py | |
| parent | a2c06140b92a0fde8587e7a413014701cf121836 (diff) | |
| download | linux-929d8490f8790164f5f63671c1c58d6c50411cb2.tar.gz linux-929d8490f8790164f5f63671c1c58d6c50411cb2.tar.bz2 linux-929d8490f8790164f5f63671c1c58d6c50411cb2.zip | |
ARM: dts: am335x-bone-common: Increase MDIO reset deassert delay to 50ms
Commit b9bf5612610aa7e3 ("ARM: dts: am335x-bone-common: Increase MDIO
reset deassert time") already increased the MDIO reset deassert delay
from 6.5 to 13 ms, but this may still cause Ethernet PHY probe failures:
SMSC LAN8710/LAN8720 4a101000.mdio:00: probe with driver SMSC LAN8710/LAN8720 failed with error -5
On BeagleBone Black Rev. C3, ETH_RESETn is controlled by an open-drain
AND gate. It is pulled high by a 10K resistor, and has a 4.7µF
capacitor to ground, giving an RC time constant of 47ms. As it takes
0.7RC to charge the capacitor above the threshold voltage of a CMOS
input (VDD/2), the delay should be at least 33ms. Considering the
typical tolerance of 20% on capacitors, 40ms would be safer. Add an
additional safety margin and settle for 50ms.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/9002a58daa1b2983f39815b748ee9d2f8dcc4829.1730366936.git.geert+renesas@glider.be
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions