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| author | Yongqiang Niu <yongqiang.niu@mediatek.com> | 2019-03-27 14:19:18 +0800 |
|---|---|---|
| committer | CK Hu <ck.hu@mediatek.com> | 2019-05-29 14:54:38 +0800 |
| commit | 937f861def1a1d49abb92e041efaa5c259281fbf (patch) | |
| tree | df69ff426dc5473272bff32ae2bb41f6dc4c6970 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | a188339ca5a396acc588e5851ed7e19f66b0ebd9 (diff) | |
| download | linux-937f861def1a1d49abb92e041efaa5c259281fbf.tar.gz linux-937f861def1a1d49abb92e041efaa5c259281fbf.tar.bz2 linux-937f861def1a1d49abb92e041efaa5c259281fbf.zip | |
drm/mediatek: adjust ddp clock control flow
display hardware clock will not unprepare when
crtc is disable, until crtc is destroyed.
with this patch, hard clock will disable and unprepare
at the same time.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions