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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2024-01-23 11:44:15 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-01-31 11:14:53 +0100 |
| commit | 78ed252953e5bdd0b3b0dd689502d5213cb6348b (patch) | |
| tree | 9dcafddaf1f2ea877114b40c3ae09975664e078b /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 292d3079abf333540fef06c1533d7c21c6d21390 (diff) | |
| download | linux-78ed252953e5bdd0b3b0dd689502d5213cb6348b.tar.gz linux-78ed252953e5bdd0b3b0dd689502d5213cb6348b.tar.bz2 linux-78ed252953e5bdd0b3b0dd689502d5213cb6348b.zip | |
clk: renesas: r9a07g043: Add clock and reset entries for CRU
Add CRU clock and reset entries to CPG driver.
CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
sequence for the CRU block hence add these clocks to
r9a07g043_no_pm_mod_clks[] array and pass it as part of CPG data for
RZ/G2UL SoCs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240123114415.290918-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions