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| author | Christophe Kerello <christophe.kerello@foss.st.com> | 2024-02-19 15:05:05 +0100 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2024-02-26 11:36:27 +0100 |
| commit | 0bfad3b3561d6f219b768d2a4265642ee9d31b1d (patch) | |
| tree | 25771724ddf7e06ef758f2af422950cf762c4f18 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | a9ae475cc60d908dfd232d1c064fc34ec51d3228 (diff) | |
| download | linux-0bfad3b3561d6f219b768d2a4265642ee9d31b1d.tar.gz linux-0bfad3b3561d6f219b768d2a4265642ee9d31b1d.tar.bz2 linux-0bfad3b3561d6f219b768d2a4265642ee9d31b1d.zip | |
mtd: rawnand: stm32_fmc2: add MP25 support
FMC2 IP supports up to 4 chip select. On MP1 SoC, only 2 of them are
available when on MP25 SoC, the 4 chip select are available.
Let's use a platform data structure for parameters that will differ.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20240219140505.85794-4-christophe.kerello@foss.st.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions