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| author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2023-10-17 09:42:36 -0500 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2023-12-11 15:21:35 +0100 |
| commit | 57cdb720eaa5c4b2fcf04ba6ff6a26f638b0b474 (patch) | |
| tree | 489afc87bace83d6298b41061d7631695c469182 /scripts/gdb/linux/tasks.py | |
| parent | 9abe6c55354db38f0906fcaf4e1c1644c26cd624 (diff) | |
| download | linux-57cdb720eaa5c4b2fcf04ba6ff6a26f638b0b474.tar.gz linux-57cdb720eaa5c4b2fcf04ba6ff6a26f638b0b474.tar.bz2 linux-57cdb720eaa5c4b2fcf04ba6ff6a26f638b0b474.zip | |
iommu/amd: Do not flush IRTE when only updating isRun and destination fields
According to the recent update in the AMD IOMMU spec [1], the IsRun and
Destination fields of the Interrupt Remapping Table Entry (IRTE) are not
cached by the IOMMU hardware.
Therefore, do not issue the INVALIDATE_INTERRUPT_TABLE command when
updating IRTE[IsRun] and IRTE[Destination] when IRTE[GuestMode]=1, which
should help improve IOMMU AVIC/x2AVIC performance.
References:
[1] AMD IOMMU Spec Revision (Rev 3.08-PUB)
(Link: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_IOMMU.pdf)
Cc: Joao Martins <joao.m.martins@oracle.com>
Cc: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Tested-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
Link: https://lore.kernel.org/r/20231017144236.8287-1-suravee.suthikulpanit@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
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