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authorJon Hunter <jonathanh@nvidia.com>2022-10-28 13:33:56 +0100
committerThierry Reding <thierry.reding@gmail.com>2022-11-09 18:30:52 +0100
commit5eccd0d9fabc4d2ab8d2a0c056fb1d7e2ff892fc (patch)
tree52463d019626acb23a3ca690a6c870b3564632d3 /drivers/pwm/pwm-sifive.c
parentf271946117dde2ca8741b8138b347b2d68e6ad56 (diff)
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pwm: tegra: Ensure the clock rate is not less than needed
When dynamically scaling the PWM clock, the function dev_pm_opp_set_rate() may set the PWM clock to a rate that is lower than what is required. The clock rate requested when calling dev_pm_opp_set_rate() is the minimum clock rate that is needed to drive the PWM to achieve the required period. Hence, if the actual clock rate is less than the requested clock rate, then the required period cannot be achieved and configuring the PWM fails. Fix this by calling clk_round_rate() to check if the clock rate that will be provided is sufficient and if not, double the required clock rate to ensure the required period can be attained. Fixes: 8c193f4714df ("pwm: tegra: Optimize period calculation") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm/pwm-sifive.c')
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