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| author | David Lechner <dlechner@baylibre.com> | 2024-10-09 16:11:49 -0500 |
|---|---|---|
| committer | Uwe Kleine-König <ukleinek@kernel.org> | 2024-10-25 11:42:36 +0200 |
| commit | 2e82d58c7ba8f7b4bb273ca5859b682b65654f9e (patch) | |
| tree | fc19b4d8c9f3a33aa17825e898d692db6e972dce /drivers/pwm/pwm-axi-pwmgen.c | |
| parent | 3c25a3d0769d13c448780b3db91104460502682d (diff) | |
| download | linux-2e82d58c7ba8f7b4bb273ca5859b682b65654f9e.tar.gz linux-2e82d58c7ba8f7b4bb273ca5859b682b65654f9e.tar.bz2 linux-2e82d58c7ba8f7b4bb273ca5859b682b65654f9e.zip | |
pwm: axi-pwmgen: Rename 0x10 register
Rename the 0x10 register from REG_CONFIG to REG_RSTN. Also rename the
associated bit macros accordingly.
While touching this, move the bit macros close to the register address
macro for better organization.
According to [1], the name of the 0x10 register is REG_RSTN, and there
is a different register named REG_CONFIG (0x18). So we should not be
using REG_CONFIG for the 0x10 register to avoid confusion.
[1]: http://analogdevicesinc.github.io/hdl/library/axi_pwm_gen/index.html
Signed-off-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Nuno Sa <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20241009-pwm-axi-pwmgen-enable-force_align-v1-1-5d6ad8cbf5b4@baylibre.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
Diffstat (limited to 'drivers/pwm/pwm-axi-pwmgen.c')
| -rw-r--r-- | drivers/pwm/pwm-axi-pwmgen.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c index 6e56ceb23d18..e1ddeaa4998b 100644 --- a/drivers/pwm/pwm-axi-pwmgen.c +++ b/drivers/pwm/pwm-axi-pwmgen.c @@ -9,7 +9,7 @@ * * Limitations: * - The writes to registers for period and duty are shadowed until - * LOAD_CONFIG is written to AXI_PWMGEN_REG_CONFIG, at which point + * LOAD_CONFIG is written to AXI_PWMGEN_REG_RSTN, at which point * they take effect. * - Writing LOAD_CONFIG also has the effect of re-synchronizing all * enabled channels, which could cause glitching on other channels. It @@ -33,14 +33,14 @@ #define AXI_PWMGEN_REG_ID 0x04 #define AXI_PWMGEN_REG_SCRATCHPAD 0x08 #define AXI_PWMGEN_REG_CORE_MAGIC 0x0C -#define AXI_PWMGEN_REG_CONFIG 0x10 +#define AXI_PWMGEN_REG_RSTN 0x10 +#define AXI_PWMGEN_REG_RSTN_LOAD_CONFIG BIT(1) +#define AXI_PWMGEN_REG_RSTN_RESET BIT(0) #define AXI_PWMGEN_REG_NPWM 0x14 #define AXI_PWMGEN_CHX_PERIOD(ch) (0x40 + (4 * (ch))) #define AXI_PWMGEN_CHX_DUTY(ch) (0x80 + (4 * (ch))) #define AXI_PWMGEN_CHX_OFFSET(ch) (0xC0 + (4 * (ch))) #define AXI_PWMGEN_REG_CORE_MAGIC_VAL 0x601A3471 /* Identification number to test during setup */ -#define AXI_PWMGEN_LOAD_CONFIG BIT(1) -#define AXI_PWMGEN_REG_CONFIG_RESET BIT(0) struct axi_pwmgen_ddata { struct regmap *regmap; @@ -152,7 +152,7 @@ static int axi_pwmgen_write_waveform(struct pwm_chip *chip, if (ret) return ret; - return regmap_write(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_LOAD_CONFIG); + return regmap_write(regmap, AXI_PWMGEN_REG_RSTN, AXI_PWMGEN_REG_RSTN_LOAD_CONFIG); } static int axi_pwmgen_read_waveform(struct pwm_chip *chip, @@ -223,7 +223,7 @@ static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev) } /* Enable the core */ - ret = regmap_clear_bits(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_REG_CONFIG_RESET); + ret = regmap_clear_bits(regmap, AXI_PWMGEN_REG_RSTN, AXI_PWMGEN_REG_RSTN_RESET); if (ret) return ret; |