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| author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2021-06-08 12:25:38 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-06-08 14:37:16 -0700 |
| commit | 5a8f09748ee79f2ef28e560bd095587a0e204b3d (patch) | |
| tree | b8a5b6e97679f0f214a0726b6ad11db5723788fb /drivers/net/dsa/sja1105/sja1105_main.c | |
| parent | ceec8bc0988dca7bdbf7421f01f8d46949bdbdeb (diff) | |
| download | linux-5a8f09748ee79f2ef28e560bd095587a0e204b3d.tar.gz linux-5a8f09748ee79f2ef28e560bd095587a0e204b3d.tar.bz2 linux-5a8f09748ee79f2ef28e560bd095587a0e204b3d.zip | |
net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX
The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY
and multiple 100base-T1 PHYs.
The access procedure for the 100base-T1 PHYs is also different than it
is for the 100base-TX one. So we register 2 MDIO buses, one for the
base-TX and the other for the base-T1. Each bus has an OF node which is
a child of the "mdio" subnode of the switch, and they are recognized by
compatible string.
Cc: Russell King <linux@armlinux.org.uk>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/sja1105/sja1105_main.c')
| -rw-r--r-- | drivers/net/dsa/sja1105/sja1105_main.c | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/drivers/net/dsa/sja1105/sja1105_main.c b/drivers/net/dsa/sja1105/sja1105_main.c index 801cf47d9572..3b031864ad74 100644 --- a/drivers/net/dsa/sja1105/sja1105_main.c +++ b/drivers/net/dsa/sja1105/sja1105_main.c @@ -168,6 +168,15 @@ static int sja1105_init_mii_settings(struct sja1105_private *priv) continue; switch (priv->phy_mode[i]) { + case PHY_INTERFACE_MODE_INTERNAL: + if (priv->info->internal_phy[i] == SJA1105_NO_PHY) + goto unsupported; + + mii->xmii_mode[i] = XMII_MODE_MII; + if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX) + mii->special[i] = true; + + break; case PHY_INTERFACE_MODE_REVMII: role = XMII_PHY; fallthrough; @@ -3109,11 +3118,19 @@ static int sja1105_setup(struct dsa_switch *ds) dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc); return rc; } + + rc = sja1105_mdiobus_register(ds); + if (rc < 0) { + dev_err(ds->dev, "Failed to register MDIO bus: %pe\n", + ERR_PTR(rc)); + goto out_ptp_clock_unregister; + } + /* Create and send configuration down to device */ rc = sja1105_static_config_load(priv); if (rc < 0) { dev_err(ds->dev, "Failed to load static config: %d\n", rc); - goto out_ptp_clock_unregister; + goto out_mdiobus_unregister; } /* Configure the CGU (PHY link modes and speeds) */ rc = priv->info->clocking_setup(priv); @@ -3156,6 +3173,8 @@ static int sja1105_setup(struct dsa_switch *ds) out_devlink_teardown: sja1105_devlink_teardown(ds); +out_mdiobus_unregister: + sja1105_mdiobus_unregister(ds); out_ptp_clock_unregister: sja1105_ptp_clock_unregister(ds); out_static_config_free: |