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| author | Shyam Sundar S K <Shyam-sundar.S-k@amd.com> | 2024-08-29 14:47:13 +0530 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2024-09-05 18:34:09 +0200 |
| commit | ced86959d28cc26bbfc5f2fd6e37407637c20e11 (patch) | |
| tree | 1c6b4bfa566f6a1294c0a5b9aac00104562a127f /drivers/i3c/master/mipi-i3c-hci/core.c | |
| parent | 46d4daa517e91a197ad253c1d81de29e8e2980be (diff) | |
| download | linux-ced86959d28cc26bbfc5f2fd6e37407637c20e11.tar.gz linux-ced86959d28cc26bbfc5f2fd6e37407637c20e11.tar.bz2 linux-ced86959d28cc26bbfc5f2fd6e37407637c20e11.zip | |
i3c: mipi-i3c-hci: Add a quirk to set Response buffer threshold
The current driver sets the response buffer threshold value to 1
(N+1, 2 DWORDS) in the QUEUE THRESHOLD register. However, the AMD
I3C controller only generates interrupts when the response buffer
threshold value is set to 0 (1 DWORD).
Therefore, a quirk is added to set the response buffer threshold value
to 0.
Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: Guruvendra Punugupati <Guruvendra.Punugupati@amd.com>
Signed-off-by: Guruvendra Punugupati <Guruvendra.Punugupati@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20240829091713.736217-7-Shyam-sundar.S-k@amd.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'drivers/i3c/master/mipi-i3c-hci/core.c')
| -rw-r--r-- | drivers/i3c/master/mipi-i3c-hci/core.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index f9ce0ee2cfd5..a82c47c9986d 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -146,6 +146,10 @@ static int i3c_hci_bus_init(struct i3c_master_controller *m) if (ret) return ret; + /* Set RESP_BUF_THLD to 0(n) to get 1(n+1) response */ + if (hci->quirks & HCI_QUIRK_RESP_BUF_THLD) + amd_set_resp_buf_thld(hci); + reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE); DBG("HC_CONTROL = %#x", reg_read(HC_CONTROL)); @@ -842,7 +846,7 @@ static const __maybe_unused struct of_device_id i3c_hci_of_match[] = { MODULE_DEVICE_TABLE(of, i3c_hci_of_match); static const struct acpi_device_id i3c_hci_acpi_match[] = { - { "AMDI5017", HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING }, + { "AMDI5017", HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING | HCI_QUIRK_RESP_BUF_THLD }, {} }; MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); |