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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2017-10-27 22:31:26 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2017-10-30 19:56:51 +0200 |
| commit | bb911536f07e5ed9147e3acf55a2cd72dffff70d (patch) | |
| tree | e8fa39016cfa32d87d6cd8cfb22ac8c4b88fca71 /drivers/gpu/drm/i915/intel_dp_mst.c | |
| parent | 0fce04c8764bd0d6ef9b4488460a5a880afb1c73 (diff) | |
| download | linux-bb911536f07e5ed9147e3acf55a2cd72dffff70d.tar.gz linux-bb911536f07e5ed9147e3acf55a2cd72dffff70d.tar.bz2 linux-bb911536f07e5ed9147e3acf55a2cd72dffff70d.zip | |
drm/i915: Eliminate pll->state usage from bxt_calc_pll_link()
We should be using the DPLL hw state we got from the current crtc state
to determine the corresponding port clock frequency rather than getting
it via the current state programmed into the DPLL.
v2: Rebase due to intel_dpll_id changes
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171027193128.14483-5-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions