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| author | Lewis Huang <Lewis.Huang@amd.com> | 2019-09-05 15:33:58 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-10-10 19:32:03 -0500 |
| commit | f537d474df15393ad25721f5203ce16ed3596d66 (patch) | |
| tree | 3ea2943d295e52b149889bdc9ff0b5c619fbc27c /drivers/gpu/drm/amd/display/modules/freesync/freesync.c | |
| parent | d832fc3b182045185e3dd92e20ac31c84be68da7 (diff) | |
| download | linux-f537d474df15393ad25721f5203ce16ed3596d66.tar.gz linux-f537d474df15393ad25721f5203ce16ed3596d66.tar.bz2 linux-f537d474df15393ad25721f5203ce16ed3596d66.zip | |
drm/amd/display: check phy dpalt lane count config
[Why]
Type-c PHY config is not align with dpcd lane count.
When those values didn't match, it cause driver do
link training with 4 lane but phy only can output 2 lane.
The link trainig always fail.
[How]
1. Modify get_max_link_cap function. According DPALT_DP4
to update max lane count.
2. Add dp_mst_verify_link_cap to handle MST case because
we didn't call dp_mst_verify_link_cap for MST case.
Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c')
0 files changed, 0 insertions, 0 deletions