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author | Dave Airlie <airlied@redhat.com> | 2019-02-11 14:04:05 +1000 |
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committer | Dave Airlie <airlied@redhat.com> | 2019-02-11 14:04:20 +1000 |
commit | f4bc54b532a62d8bee421ca06adb6d1b3e7ffaa9 (patch) | |
tree | 3b835f9bed6bd236fa1a6d5d0add836f25ca8262 /drivers/gpu/drm/amd/display/dc/dc.h | |
parent | 5ea3998d56346975c2701df18fb5b6e3ab5c8d9e (diff) | |
parent | 0461221316ec21e0a535a35fba3feb6ba75706e6 (diff) | |
download | linux-f4bc54b532a62d8bee421ca06adb6d1b3e7ffaa9.tar.gz linux-f4bc54b532a62d8bee421ca06adb6d1b3e7ffaa9.tar.bz2 linux-f4bc54b532a62d8bee421ca06adb6d1b3e7ffaa9.zip |
Merge branch 'drm-next-5.1' of git://people.freedesktop.org/~agd5f/linux into drm-next
Updates for 5.1:
- GDS fixes
- Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES interface
- GPUVM fixes
- PCIE DPM switching fixes for vega20
- Vega10 uclk DPM regression fix
- DC Freesync fixes
- DC ABM fixes
- Various DC cleanups
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190208210214.27666-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 8391bc39b7a9..1a7fd6aa77eb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -39,7 +39,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.15" +#define DC_VER "3.2.17" #define MAX_SURFACES 3 #define MAX_STREAMS 6 @@ -255,6 +255,7 @@ struct dc_debug_options { bool scl_reset_length10; bool hdmi20_disable; bool skip_detection_link_training; + unsigned int force_odm_combine; //bit vector based on otg inst unsigned int force_fclk_khz; }; @@ -264,7 +265,6 @@ struct dc_debug_data { uint32_t auxErrorCount; }; - struct dc_state; struct resource_pool; struct dce_hwseq; @@ -594,6 +594,10 @@ struct dc_validation_set { uint8_t plane_count; }; +bool dc_validate_seamless_boot_timing(struct dc *dc, + const struct dc_sink *sink, + struct dc_crtc_timing *crtc_timing); + enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); |