Merge tag 'amd-drm-next-6.11-2024-06-07' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-6.11-2024-06-07:

amdgpu:
- DCN 4.0.x support
- DCN 3.5 updates
- GC 12.0 support
- DP MST fixes
- Cursor fixes
- MES11 updates
- MMHUB 4.1 support
- DML2 Updates
- DCN 3.1.5 fixes
- IPS fixes
- Various code cleanups
- GMC 12.0 support
- SDMA 7.0 support
- SMU 13 updates
- SR-IOV fixes
- VCN 5.x fixes
- MES12 support
- SMU 14.x updates
- Devcoredump improvements
- Fixes for HDP flush on platforms with >4k pages
- GC 9.4.3 fixes
- RAS ACA updates
- Silence UBSAN flex array warnings
- MMHUB 3.3 updates

amdkfd:
- Contiguous VRAM allocations
- GC 12.0 support
- SDMA 7.0 support
- SR-IOV fixes

radeon:
- Backlight workaround for iMac
- Silence UBSAN flex array warnings

UAPI:
- GFX12 modifier and DCC support
  Proposed Mesa changes:
  https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29510
- KFD GFX ALU exceptions
  Proposed ROCdebugger changes:
  https://github.com/ROCm/ROCdbgapi/commit/08c760622b6601abf906f75abbc5e21d9fd425df
  https://github.com/ROCm/ROCgdb/commit/944fe1c1414a68700414e86e32273b6bfa62ba6f
- KFD Contiguous VRAM allocation flag
  Proposed ROCr/HIP changes:
  https://github.com/ROCm/ROCT-Thunk-Interface/commit/f7b4a269914a3ab4f1e2453c2879adb97b5cc9e5
  https://github.com/ROCm/ROCR-Runtime/pull/214/commits/26e8530d05a775872cb06dde6693db72be0c454a
  https://github.com/ROCm/clr/commit/1d48f2a1ab38b632919c4b7274899b3faf4279ff

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607195900.902537-1-alexander.deucher@amd.com

1 files changed, 2 insertions, 73 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
index bfe61d86ee6c..6d6350f220b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
@@ -71,7 +71,7 @@ static void umc_v12_0_reset_error_count(struct amdgpu_device *adev)
 
 bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status)
 {
-	dev_info(adev->dev,
+	dev_dbg(adev->dev,
 		"MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, PCC:%llu, UC:%llu, TCC:%llu\n",
 		mc_umc_status,
 		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val),
@@ -376,77 +376,6 @@ static int umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev,
 	return 0;
 }
 
-#ifdef TO_BE_REMOVED
-static void umc_v12_0_ecc_info_query_ras_error_count(struct amdgpu_device *adev,
-					void *ras_error_status)
-{
-	struct ras_query_context qctx;
-
-	memset(&qctx, 0, sizeof(qctx));
-	qctx.event_id = amdgpu_ras_acquire_event_id(adev, amdgpu_ras_intr_triggered() ?
-						    RAS_EVENT_TYPE_ISR : RAS_EVENT_TYPE_INVALID);
-
-	amdgpu_mca_smu_log_ras_error(adev,
-		AMDGPU_RAS_BLOCK__UMC, AMDGPU_MCA_ERROR_TYPE_CE, ras_error_status, &qctx);
-	amdgpu_mca_smu_log_ras_error(adev,
-		AMDGPU_RAS_BLOCK__UMC, AMDGPU_MCA_ERROR_TYPE_UE, ras_error_status, &qctx);
-}
-
-static void umc_v12_0_ecc_info_query_ras_error_address(struct amdgpu_device *adev,
-					void *ras_error_status)
-{
-	struct ras_err_node *err_node;
-	uint64_t mc_umc_status;
-	struct ras_err_info *err_info;
-	struct ras_err_addr *mca_err_addr, *tmp;
-	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
-	struct ta_ras_query_address_input addr_in;
-
-	for_each_ras_error(err_node, err_data) {
-		err_info = &err_node->err_info;
-		if (list_empty(&err_info->err_addr_list))
-			continue;
-
-		addr_in.ma.node_inst = err_info->mcm_info.die_id;
-		addr_in.ma.socket_id = err_info->mcm_info.socket_id;
-
-		list_for_each_entry_safe(mca_err_addr, tmp, &err_info->err_addr_list, node) {
-			mc_umc_status = mca_err_addr->err_status;
-			if (mc_umc_status &&
-				(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status) ||
-				 umc_v12_0_is_deferred_error(adev, mc_umc_status))) {
-				uint64_t mca_addr, err_addr, mca_ipid;
-				uint32_t InstanceIdLo;
-
-				mca_addr = mca_err_addr->err_addr;
-				mca_ipid = mca_err_addr->err_ipid;
-
-				err_addr = REG_GET_FIELD(mca_addr,
-							MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
-				InstanceIdLo = REG_GET_FIELD(mca_ipid, MCMP1_IPIDT0, InstanceIdLo);
-
-				addr_in.ma.err_addr = err_addr;
-				addr_in.ma.ch_inst = MCA_IPID_LO_2_UMC_CH(InstanceIdLo);
-				addr_in.ma.umc_inst = MCA_IPID_LO_2_UMC_INST(InstanceIdLo);
-
-				dev_info(adev->dev, "UMC:IPID:0x%llx, aid:%d, inst:%d, ch:%d, err_addr:0x%llx\n",
-					mca_ipid,
-					err_info->mcm_info.die_id,
-					MCA_IPID_LO_2_UMC_INST(InstanceIdLo),
-					MCA_IPID_LO_2_UMC_CH(InstanceIdLo),
-					err_addr);
-
-				umc_v12_0_convert_error_address(adev,
-					err_data, &addr_in);
-			}
-
-			/* Delete error address node from list and free memory */
-			amdgpu_ras_del_mca_err_addr(err_info, mca_err_addr);
-		}
-	}
-}
-#endif
-
 static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev,
 			enum amdgpu_mca_error_type type, void *ras_error_status)
 {
@@ -575,7 +504,7 @@ static int umc_v12_0_update_ecc_status(struct amdgpu_device *adev,
 	err_addr = REG_GET_FIELD(addr,
 				MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
 
-	dev_info(adev->dev,
+	dev_dbg(adev->dev,
 		"UMC:IPID:0x%llx, socket:%llu, aid:%llu, inst:%llu, ch:%llu, err_addr:0x%llx\n",
 		ipid,
 		MCA_IPID_2_SOCKET_ID(ipid),