diff options
| author | Jani Nikula <jani.nikula@intel.com> | 2024-06-19 11:38:31 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2024-06-19 11:38:31 +0300 |
| commit | d754ed2821fd9675d203cb73c4afcd593e28b7d0 (patch) | |
| tree | cd16683cd956a7c334d7e1b3baf02e2e7baa729c /drivers/gpu/drm/amd/amdgpu/soc15.c | |
| parent | dcaacff03a9fa2838f936e1009b4b7ad56807152 (diff) | |
| parent | 1ddaaa244021aba8496536a6627b4ad2bc0f936a (diff) | |
| download | linux-d754ed2821fd9675d203cb73c4afcd593e28b7d0.tar.gz linux-d754ed2821fd9675d203cb73c4afcd593e28b7d0.tar.bz2 linux-d754ed2821fd9675d203cb73c4afcd593e28b7d0.zip | |
Merge drm/drm-next into drm-intel-next
Sync to v6.10-rc3.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.c | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 170f02e96717..8d16dacdc172 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -326,7 +326,8 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev) if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) || - amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6)) + amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) || + amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14)) return 10000; if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1)) @@ -554,6 +555,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev) return AMD_RESET_METHOD_MODE2; break; case IP_VERSION(13, 0, 6): + case IP_VERSION(13, 0, 14): /* Use gpu_recovery param to target a reset method. * Enable triggering of GPU reset only if specified * by module parameter. @@ -929,13 +931,9 @@ static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = static int soc15_common_early_init(void *handle) { -#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (!amdgpu_sriov_vf(adev)) { - adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; - adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; - } + adev->nbio.funcs->set_reg_remap(adev); adev->smc_rreg = NULL; adev->smc_wreg = NULL; adev->pcie_rreg = &amdgpu_device_indirect_rreg; @@ -1172,6 +1170,7 @@ static int soc15_common_early_init(void *handle) adev->external_rev_id = adev->rev_id + 0x3c; break; case IP_VERSION(9, 4, 3): + case IP_VERSION(9, 4, 4): adev->asic_funcs = &aqua_vanjaram_asic_funcs; adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | @@ -1183,12 +1182,8 @@ static int soc15_common_early_init(void *handle) AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG | AMD_PG_SUPPORT_JPEG; + /*TODO: need a new external_rev_id for GC 9.4.4? */ adev->external_rev_id = adev->rev_id + 0x46; - /* GC 9.4.3 uses MMIO register region hole at a different offset */ - if (!amdgpu_sriov_vf(adev)) { - adev->rmmio_remap.reg_offset = 0x1A000; - adev->rmmio_remap.bus_addr = adev->rmmio_base + 0x1A000; - } break; default: /* FIXME: not supported yet */ @@ -1458,7 +1453,8 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags) adev->hdp.funcs->get_clock_gating_state(adev, flags); if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) && - (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))) { + (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) && + (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) { /* AMD_CG_SUPPORT_DRM_MGCG */ data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); if (!(data & 0x01000000)) |