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| author | Jani Nikula <jani.nikula@intel.com> | 2024-06-19 11:38:31 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2024-06-19 11:38:31 +0300 |
| commit | d754ed2821fd9675d203cb73c4afcd593e28b7d0 (patch) | |
| tree | cd16683cd956a7c334d7e1b3baf02e2e7baa729c /drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | |
| parent | dcaacff03a9fa2838f936e1009b4b7ad56807152 (diff) | |
| parent | 1ddaaa244021aba8496536a6627b4ad2bc0f936a (diff) | |
| download | linux-d754ed2821fd9675d203cb73c4afcd593e28b7d0.tar.gz linux-d754ed2821fd9675d203cb73c4afcd593e28b7d0.tar.bz2 linux-d754ed2821fd9675d203cb73c4afcd593e28b7d0.zip | |
Merge drm/drm-next into drm-intel-next
Sync to v6.10-rc3.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c index df218d5ca775..fa479dfa1ec1 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c @@ -339,10 +339,6 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev) if (def != data) WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); - - if (amdgpu_sriov_vf(adev)) - adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, - mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; } #define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1 @@ -553,6 +549,20 @@ static void nbio_v2_3_clear_doorbell_interrupt(struct amdgpu_device *adev) } } +#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) + +static void nbio_v2_3_set_reg_remap(struct amdgpu_device *adev) +{ + if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { + adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; + adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; + } else { + adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, + mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; + adev->rmmio_remap.bus_addr = 0; + } +} + const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset, .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset, @@ -577,4 +587,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { .apply_lc_spc_mode_wa = nbio_v2_3_apply_lc_spc_mode_wa, .apply_l1_link_width_reconfig_wa = nbio_v2_3_apply_l1_link_width_reconfig_wa, .clear_doorbell_interrupt = nbio_v2_3_clear_doorbell_interrupt, + .set_reg_remap = nbio_v2_3_set_reg_remap, }; |