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| author | Dave Airlie <airlied@redhat.com> | 2021-08-26 12:18:26 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2021-08-26 12:18:27 +1000 |
| commit | 697b6e28d0e8ed87a0bc1bf1d2c1a3f3abbce9d3 (patch) | |
| tree | 2bf812fa3e170f66b4a5d35e8dd968a5389a5744 /drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | |
| parent | 397ab98e2d69cede84444a28eab77a171983d14e (diff) | |
| parent | 90a9266269eb9f71af1f323c33e1dca53527bd22 (diff) | |
| download | linux-697b6e28d0e8ed87a0bc1bf1d2c1a3f3abbce9d3.tar.gz linux-697b6e28d0e8ed87a0bc1bf1d2c1a3f3abbce9d3.tar.bz2 linux-697b6e28d0e8ed87a0bc1bf1d2c1a3f3abbce9d3.zip | |
Merge tag 'amd-drm-next-5.15-2021-08-20' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.15-2021-08-20:
amdgpu:
- embed hw fence into job
- Misc SMU fixes
- PSP TA code cleanup
- RAS fixes
- PWM fan speed fixes
- DC workqueue cleanups
- SR-IOV fixes
- gfxoff delayed work fix
- Pin domain check fix
amdkfd:
- SVM fixes
radeon:
- Code cleanup
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210820172335.4190-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_object.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index d15eee98204d..7734c10ae74e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -920,11 +920,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, return -EINVAL; } - /* This assumes only APU display buffers are pinned with (VRAM|GTT). - * See function amdgpu_display_supported_domains() - */ - domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); - if (bo->tbo.pin_count) { uint32_t mem_type = bo->tbo.resource->mem_type; uint32_t mem_flags = bo->tbo.resource->placement; @@ -949,6 +944,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, return 0; } + /* This assumes only APU display buffers are pinned with (VRAM|GTT). + * See function amdgpu_display_supported_domains() + */ + domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); + if (bo->tbo.base.import_attach) dma_buf_pin(bo->tbo.base.import_attach); |