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| author | Shashank Sharma <shashank.sharma@amd.com> | 2021-02-13 22:07:24 +0530 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-23 23:01:42 -0400 |
| commit | e36ccf9a96aab1e3a7cb2ed36935eaea83b64710 (patch) | |
| tree | 45a4a26149b309f678dc8cc6ae67723d5824f9c3 /drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | |
| parent | 0b46bc3a9d17ddc98d0cb7cb78e9b9b77e9162a3 (diff) | |
| download | linux-e36ccf9a96aab1e3a7cb2ed36935eaea83b64710.tar.gz linux-e36ccf9a96aab1e3a7cb2ed36935eaea83b64710.tar.bz2 linux-e36ccf9a96aab1e3a7cb2ed36935eaea83b64710.zip | |
drm/amdgpu: Set GTT_USWC flag to enable freesync v2
This patch sets 'AMDGPU_GEM_CREATE_CPU_GTT_USWC' as input
parameter flag, during object creation of an imported DMA
buffer.
In absence of this flag:
1. Function amdgpu_display_supported_domains() doesn't add
AMDGPU_GEM_DOMAIN_GTT as supported domain.
2. Due to which, Function amdgpu_display_user_framebuffer_create()
refuses to create framebuffer for imported DMA buffers.
3. Due to which, AddFB() IOCTL fails.
4. Due to which, amdgpu_present_check_flip() check fails in DDX
5. Due to which DDX driver doesn't allow flips (goes to blitting)
6. Due to which setting Freesync/VRR property fails for PRIME buffers.
So, this patch finally enables Freesync with PRIME buffer offloading.
v2 (chk): instead of just checking the flag we copy it over if the
exporter is an amdgpu device as well.
Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c')
0 files changed, 0 insertions, 0 deletions