From ec341e0f4a02040ee8d6ef156f8bf02c5aa5c511 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Mon, 20 Mar 2023 16:47:21 -0400 Subject: drm/amd/display: add extra dc odm debug options [Why & How] Add options for dc odm debug. Reviewed-by: Ariel Bernstein Acked-by: Qingqing Zhuo Signed-off-by: Dmytro Laktyushkin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 23ee63b98dcd..3595149deceb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -879,6 +879,8 @@ struct dc_debug_options { uint32_t fpo_vactive_margin_us; bool disable_fpo_vactive; bool disable_boot_optimizations; + bool override_odm_optimization; + bool minimize_dispclk_using_odm; }; struct gpu_info_soc_bounding_box_v1_0; -- cgit From f0c5f9ebbc4cfd6b9611b8a5d9fb208c5f60e3e6 Mon Sep 17 00:00:00 2001 From: Michael Mityushkin Date: Thu, 30 Mar 2023 11:35:08 -0400 Subject: drm/amd/display: Apply correct panel mode when reinitializing hardware [Why] When link training during engine recovery, ASSR might fail causing panel mode to be reset to default. This should not happen for eDP as it will prevent the panel from turning back on. [How] Added dp_panel_mode to struct dc_link to remember previously applied panel mode. Do not reset panel mode to default while performing link training if previously used panel mode = eDP. Reviewed-by: Nicholas Kazlauskas Acked-by: Qingqing Zhuo Signed-off-by: Michael Mityushkin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 3595149deceb..3b53f36029d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1456,6 +1456,7 @@ struct dc_link { struct ddc_service *ddc; + enum dp_panel_mode panel_mode; bool aux_mode; /* Private to DC core */ -- cgit From 3306ba4b60b2f3d9ac6bddc587a4d702e1ba2224 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 18 Apr 2023 00:07:18 +0200 Subject: drm/amd/display: fix is_timing_changed() prototype Three functions in the amdgpu display driver cause -Wmissing-prototype warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:1858:6: error: no previous prototype for 'is_timing_changed' [-Werror=missing-prototypes] is_timing_changed() is actually meant to be a global symbol, but needs a proper name and prototype. Fixes: 17ce8a6907f7 ("drm/amd/display: Add dsc pre-validation in atomic check") Reviewed-by: Aurabindo Pillai Signed-off-by: Arnd Bergmann Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 3b53f36029d0..edef5d181590 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -2228,4 +2228,7 @@ void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, /* Disable acc mode Interfaces */ void dc_disable_accelerated_mode(struct dc *dc); +bool dc_is_timing_changed(struct dc_stream_state *cur_stream, + struct dc_stream_state *new_stream); + #endif /* DC_INTERFACE_H_ */ -- cgit From 4371fa7795dabb422171de5e8d9fe7aa3e2edb86 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sun, 2 Apr 2023 22:20:20 -0400 Subject: drm/amd/display: 3.2.231 This DC version brings along: - FW Release 0.0.162.0 - Enable FPO+Vactivate - Support for VESA SCR - Refactor DMUB commands - Fixes in secure display, modeset, memleak and more - Picked up missed patches in history Acked-by: Qingqing Zhuo Signed-off-by: Aric Cyr Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index edef5d181590..b45974a2dec3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.230" +#define DC_VER "3.2.231" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- cgit From 9fa8cc0c444562fa19e20ca20f1c70e15b9d8c13 Mon Sep 17 00:00:00 2001 From: Michael Strauss Date: Mon, 3 Apr 2023 11:43:50 -0400 Subject: drm/amd/display: Convert Delaying Aux-I Disable To Monitor Patch [WHY] 32ms delay was added to resolve issue with a specific sink, however this same delay also introduces erroneous link training failures with certain sink devices. [HOW] Only apply the 32ms delay for offending devices instead of globally. Tested-by: Daniel Wheeler Reviewed-by: Jun Lei Acked-by: Rodrigo Siqueira Signed-off-by: Michael Strauss Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index b45974a2dec3..97747f5fde56 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -855,7 +855,6 @@ struct dc_debug_options { bool force_usr_allow; /* uses value at boot and disables switch */ bool disable_dtb_ref_clk_switch; - uint32_t fixed_vs_aux_delay_config_wa; bool extended_blank_optimization; union aux_wake_wa_options aux_wake_wa; uint32_t mst_start_top_delay; -- cgit From 267e2d8e8e60ed59e74cf888f6b74bd5202e7384 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sun, 9 Apr 2023 23:08:25 -0400 Subject: drm/amd/display: 3.2.232 Acked-by: Rodrigo Siqueira Signed-off-by: Aric Cyr Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 97747f5fde56..d6f0ecb708cd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.231" +#define DC_VER "3.2.232" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- cgit From b058e3999021e04cd16d1e487732e20ad1f4b4f6 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Mon, 10 Apr 2023 17:17:07 -0400 Subject: drm/amd/display: Enable SubVP on PSR panels if single stream Enable SubVP on PSR panels now that we have FW support Tested-by: Daniel Wheeler Reviewed-by: Jun Lei Acked-by: Rodrigo Siqueira Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d6f0ecb708cd..dc0a61ca99d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -209,6 +209,7 @@ struct dc_color_caps { struct dc_dmub_caps { bool psr; bool mclk_sw; + bool subvp_psr; }; struct dc_caps { -- cgit From 469a62938a45ef382c9cb7b9fec6c6c1fcd781c0 Mon Sep 17 00:00:00 2001 From: Gabe Teeger Date: Thu, 6 Apr 2023 17:03:06 -0400 Subject: drm/amd/display: update extended blank for dcn314 onwards [Why] Flickering and underflow was observed when testing extended blank on dcn314. [What] Vstartup is contrainted by vblank_nom, so adjusting it to include non-adjusted vtotal in its calculation during freesync video means that Vstartup is not changed when vtotal changes. This fixed the flickering + underflow. dc_extended_blank_supported function was removed because extended blank is only relevant to when zstate is supported. The increased vtotal during freesync can be passed to dml regardless of whether extended blank is supported or not, so this function is not needed. Updates were made recently in dml to the calculation of min_dst_y_next_start. Dml input for dcn314 will now always use the newer calculation for min_dst_y_next_start. Dml input for older dcn versions remains untouched. The variable optimized_min_dst_y_next_start is replaced everywhere with min_dst_y_next_start, and the updated dml allows min_dst_y_next_start to increase to an optimized value during freesync video, then return to default when freesync is disengaged. Also removed registry key for controlling extended blank feature. Tested-by: Daniel Wheeler Reviewed-by: Nicholas Kazlauskas Acked-by: Rodrigo Siqueira Signed-off-by: Gabe Teeger Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index dc0a61ca99d0..5268d98b96dc 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -2128,8 +2128,6 @@ struct dc_sink_init_data { bool converter_disable_audio; }; -bool dc_extended_blank_supported(struct dc *dc); - struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); /* Newer interfaces */ -- cgit From 87f0c16e0eeb672fb888b4e173edff0252e02757 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Mon, 17 Apr 2023 10:23:05 -0400 Subject: drm/amd/display: Enable SubVP for high refresh rate displays [Description] - Add debug option to enable SubVP for high refresh rate displays - For now limit the enabled modes based on a table in debug options - Currently disabled by default Tested-by: Daniel Wheeler Reviewed-by: Jun Lei Acked-by: Rodrigo Siqueira Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5268d98b96dc..e41107098ffe 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -881,6 +881,7 @@ struct dc_debug_options { bool disable_boot_optimizations; bool override_odm_optimization; bool minimize_dispclk_using_odm; + bool disable_subvp_high_refresh; }; struct gpu_info_soc_bounding_box_v1_0; -- cgit From 1938bcdc4b530d6413e03f238c2df56f99f17220 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Wed, 12 Apr 2023 17:06:46 -0400 Subject: drm/amd/display: Query GECC enable for SubVP disable - We want to disable SubVP if Graphics Error Correction/Correcting Code (GECC) is enabled. - After reading feature caps from DMCUB during init, use the GECC enable/disable info to determine if SubVP can be enabled or not. Tested-by: Daniel Wheeler Reviewed-by: Nicholas Kazlauskas Reviewed-by: Jun Lei Acked-by: Rodrigo Siqueira Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e41107098ffe..f52ab717ac7d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -210,6 +210,7 @@ struct dc_dmub_caps { bool psr; bool mclk_sw; bool subvp_psr; + bool gecc_enable; }; struct dc_caps { -- cgit From 612c5ad50c3e5505e674b7cc50bf6527bc0adee6 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sun, 16 Apr 2023 20:35:01 -0400 Subject: drm/amd/display: 3.2.233 This DC version brings along: - Improvements in the SubVP feature - Keep disable aux-i delay as 0 - Add p-state debugging and improvements - Fix in secure display context creation - add option to use custom backlight caps - Lowering min Z8 residency time - Restore rptr/wptr for DMCUB as workaround - Update FW feature caps struct Acked-by: Rodrigo Siqueira Signed-off-by: Aric Cyr Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f52ab717ac7d..4424e7abb801 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.232" +#define DC_VER "3.2.233" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- cgit From 5b7bee5b445785a47b781e889e51219ec35d4407 Mon Sep 17 00:00:00 2001 From: Ilya Bakoulin Date: Fri, 14 Apr 2023 12:46:48 -0400 Subject: drm/amd/display: Workaround wrong HDR colorimetry with some receivers [Why] Some scalers do not pick up color space updates unless the DP link is disabled/re-enabled which can result in incorrect/washed out HDR colors in some cases. [How] Call set_dpms_on to disable the link, re-train and re-enable with the updated output color space. Reviewed-by: Aric Cyr Acked-by: Alan Liu Signed-off-by: Ilya Bakoulin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4424e7abb801..892e3adb99d9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1506,6 +1506,7 @@ struct dc_link { /* Forced DPIA into TBT3 compatibility mode. */ bool dpia_forced_tbt3_mode; bool dongle_mode_timing_override; + bool blank_stream_on_ocs_change; } wa_flags; struct link_mst_stream_allocation_table mst_stream_alloc_table; -- cgit From 4dfa60aede755814dcfbc9a05008265d827cc98d Mon Sep 17 00:00:00 2001 From: Leo Chen Date: Thu, 13 Apr 2023 17:37:49 -0400 Subject: drm/amd/display: Adding debug option to override Z8 watermark values [Why & How] Adding debug options to override Z8 watermark values for testing purposes. Reviewed-by: Nicholas Kazlauskas Acked-by: Alan Liu Signed-off-by: Leo Chen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 892e3adb99d9..fea68383bb61 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -700,6 +700,8 @@ struct dc_virtual_addr_space_config { struct dc_bounding_box_overrides { int sr_exit_time_ns; int sr_enter_plus_exit_time_ns; + int sr_exit_z8_time_ns; + int sr_enter_plus_exit_z8_time_ns; int urgent_latency_ns; int percent_of_ideal_drambw; int dram_clock_change_latency_ns; @@ -769,6 +771,8 @@ struct dc_debug_options { int sr_enter_plus_exit_time_dpm0_ns; int sr_exit_time_ns; int sr_enter_plus_exit_time_ns; + int sr_exit_z8_time_ns; + int sr_enter_plus_exit_z8_time_ns; int urgent_latency_ns; uint32_t underflow_assert_delay_us; int percent_of_ideal_drambw; -- cgit From 124155c0bd4a4ed822c1ba246bdf5123b42c3ad9 Mon Sep 17 00:00:00 2001 From: George Shen Date: Thu, 13 Apr 2023 19:03:59 -0400 Subject: drm/amd/display: Add w/a to disable DP dual mode on certain ports [Why] Certain ports on DCN3.2 configs do not properly populate the BIOS info table flag to indicate DP dual mode is unsupported. [How] Add a workaround to disable DP dual mode on the ports with the missing BIOS info table flag. Reviewed-by: Michael Strauss Acked-by: Alan Liu Signed-off-by: George Shen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index fea68383bb61..fe60816653d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -887,6 +887,7 @@ struct dc_debug_options { bool override_odm_optimization; bool minimize_dispclk_using_odm; bool disable_subvp_high_refresh; + bool disable_dp_plus_plus_wa; }; struct gpu_info_soc_bounding_box_v1_0; -- cgit From 4ab9d5848c728e5339e382f678a5e580573b3a3a Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sun, 23 Apr 2023 22:12:05 -0400 Subject: drm/amd/display: 3.2.234 This version brings along following fixes: - FW Release 0.0.165.0 - Add w/a to disable DP dual mode on certain ports - Revert "Update scaler recout data for visual confirm" - Filter out invalid bits in pipe_fuses - Adding debug option to override Z8 watermark values - Change default Z8 watermark values - Workaround wrong HDR colorimetry with some receivers Acked-by: Alan Liu Signed-off-by: Aric Cyr Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index fe60816653d0..7e3f20a3a02f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.233" +#define DC_VER "3.2.234" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- cgit From aaa07c0d08a37bf72cd73a3119ff99dc2bfece74 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sun, 30 Apr 2023 15:54:14 -0400 Subject: drm/amd/display: Promote DAL to 3.2.235 This version brings along following fixes: - Block SubVP on displays that have pixclk > 1800Mhz - Block SubVP high refresh when VRR active fixed - Enforce 60us prefetch for 200Mhz DCFCLK modes - Check Vactive for VRR active for FPO + Vactive - Add symclk workaround during disable link output - Show the DCN/DCE version in the log - Add additional pstate registers to HW state query Acked-by: Alex Hung Signed-off-by: Aric Cyr Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7e3f20a3a02f..f4448b545d70 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.234" +#define DC_VER "3.2.235" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- cgit From 1d8355ad922423c9f765a644ed04526a6273d9ee Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Tue, 2 May 2023 09:54:56 -0400 Subject: drm/amd/display: Only skip update for DCFCLK, UCLK, FCLK on overclock [Description] - Update clocks is skipped in the GPU overclock sequence - However, we still need to update DISPCLK, DPPCLK, and DTBCLK because the GPU overclock sequence could temporarily disable ODM 2:1 combine because we disable all planes in the sequence Reviewed-by: Jun Lei Acked-by: Aurabindo Pillai Signed-off-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f4448b545d70..e89de1078964 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -272,8 +272,13 @@ struct dc_bug_wa { bool dedcn20_305_wa; bool skip_clock_update; bool lt_early_cr_pattern; + struct { + uint8_t uclk : 1; + uint8_t fclk : 1; + uint8_t dcfclk : 1; + uint8_t dcfclk_ds: 1; + } clock_update_disable_mask; }; - struct dc_dcc_surface_param { struct dc_size surface_size; enum surface_pixel_format format; -- cgit From 6ba5a269cdc9f447be882bbf99548361c8ebc254 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Tue, 2 May 2023 12:27:26 -0400 Subject: drm/amd/display: Update vactive margin and max vblank for fpo + vactive [Description] - Some 1920x1080@60hz displays have VBLANK time > 600us which we still want to accept for FPO + Vactive configs based on testing - Increase max VBLANK time to 1000us to allow these configs for FPO + Vactive - Increase minimum vactive switch margin for FPO + Vactive to 200us - Based on testing, 1920x1080@120hz can have a switch margin of ~160us which requires significantly longer FPO stretch margin (5ms) which we don't want to accept for now - Also move margins into debug option Reviewed-by: Jun Lei Reviewed-by: Nevenko Stupar Acked-by: Aurabindo Pillai Signed-off-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e89de1078964..1ebb8d3573f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -893,6 +893,8 @@ struct dc_debug_options { bool minimize_dispclk_using_odm; bool disable_subvp_high_refresh; bool disable_dp_plus_plus_wa; + uint32_t fpo_vactive_min_active_margin_us; + uint32_t fpo_vactive_max_blank_us; }; struct gpu_info_soc_bounding_box_v1_0; -- cgit From d205a800a66e46430ab93c0d450393233d39931a Mon Sep 17 00:00:00 2001 From: "Leo (Hanghong) Ma" Date: Wed, 12 Apr 2023 14:02:01 -0400 Subject: drm/amd/display: Add visual confirm color support for MCLK switch [Why && How] We would like to have visual confirm color support for MCLK switch. 1. Set visual confirm color to yellow: Vblank MCLK switch. 2. Set visual confirm color to cyan: FPO + Vblank MCLK switch. 3. Set visual confirm color to pink: Vactive MCLK switch. Reviewed-by: Jun Lei Acked-by: Aurabindo Pillai Signed-off-by: Leo (Hanghong) Ma Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 1ebb8d3573f4..8be2e6d6d888 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -426,6 +426,7 @@ enum visual_confirm { VISUAL_CONFIRM_FAMS = 7, VISUAL_CONFIRM_SWIZZLE = 9, VISUAL_CONFIRM_SUBVP = 14, + VISUAL_CONFIRM_MCLK_SWITCH = 16, }; enum dc_psr_power_opts { -- cgit From 629b8ede8b93428b8d124d343b5fbb57ab64d5a8 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Mon, 8 May 2023 00:32:41 -0400 Subject: drm/amd/display: 3.2.236 Acked-by: Aurabindo Pillai Signed-off-by: Aric Cyr Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 8be2e6d6d888..2dff1a5cf3b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.235" +#define DC_VER "3.2.236" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- cgit From f36f2648f32c184ffc285a836b1ce3757e966925 Mon Sep 17 00:00:00 2001 From: Cruise Hung Date: Tue, 9 May 2023 21:36:35 +0800 Subject: drm/amd/display: Fix DMUB debugging print issue [Why] The DMUB diagnostic data was not printed out correctly. [How] Print the DMUB diagnostic data line by line. Reviewed-by: Nicholas Kazlauskas Acked-by: Tom Chung Signed-off-by: Cruise Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 2dff1a5cf3b1..7fc087f85d39 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -2236,6 +2236,8 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, uint32_t hpd_int_enable); +void dc_print_dmub_diagnostic_data(const struct dc *dc); + /* DSC Interfaces */ #include "dc_dsc.h" -- cgit From 0d1ff99a3398ad4b7165ecd8e69d360090b32250 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Mon, 15 May 2023 00:14:00 -0400 Subject: drm/amd/display: 3.2.237 This version brings along following fixes: - Improve the message printed - Disable dcn315 pixel rate crb when scaling - Update SR watermarks for DCN314 - Fix dcn315 pixel rate crb scaling check - Reset CRTC State Before Restore from S2idle - Have Payload Properly Created After Resume - Trigger DIO FIFO resync on commit streams - Revert vblank change that causes null pointer crash - Fix possible underflow for displays with large vblank - Apply 60us prefetch for DCFCLK <= 300Mhz - Update correct DCN314 register header Acked-by: Tom Chung Signed-off-by: Aric Cyr Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7fc087f85d39..7fd9f5a9e191 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.236" +#define DC_VER "3.2.237" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- cgit From 0baae624630788862bbd654741929007971e9d5b Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Thu, 18 May 2023 11:30:44 -0400 Subject: drm/amd/display: Refactor fast update to use new HWSS build sequence [Description] - Refactor HW sequencer to use a build / execute sequence - Also move gamma updates to become fast v2: squash in build fix ("drm/amd/display: Fix guarding of 'if (dc->debug.visual_confirm)'") Acked-by: Stylon Wang Signed-off-by: Alvin Lee Reviewed-by: Jun Lei Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7fd9f5a9e191..7ded574f84ff 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -896,6 +896,7 @@ struct dc_debug_options { bool disable_dp_plus_plus_wa; uint32_t fpo_vactive_min_active_margin_us; uint32_t fpo_vactive_max_blank_us; + bool enable_legacy_fast_update; }; struct gpu_info_soc_bounding_box_v1_0; -- cgit From 3b718dcaf163d17fe907ea098c8449e0cd6bc271 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Wed, 24 May 2023 11:52:12 -0400 Subject: drm/amd/display: Filter out AC mode frequencies on DC mode systems Why: Limit maximum clock speeds to DC mode limits for DC mode systems How: Store DC mode limits when individual clocks are initialized and cap the values when building the clock table Acked-by: Stylon Wang Signed-off-by: Austin Zheng Reviewed-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/dc/dc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7ded574f84ff..360dd83b1a7a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -897,6 +897,7 @@ struct dc_debug_options { uint32_t fpo_vactive_min_active_margin_us; uint32_t fpo_vactive_max_blank_us; bool enable_legacy_fast_update; + bool disable_dc_mode_overwrite; }; struct gpu_info_soc_bounding_box_v1_0; -- cgit